The technical evolution in the field of integrated circuits has resulted in a demand for faster and more compact systems. In many applications a compact structure combined with a low weight is in itself a requirement. The technical evolution also tends towards more complex electronic systems involving a greater and greater number of components which need to communicate with each other. In order for the new systems to meet also the requirement of quick access between different components, the length of the signal paths between different components of the system must be kept within some rather small limits.
When the complexity of an electronic system grows, the lengths of the signal paths between components, which need to communicate with each other, also grow. In order not to exceed the maximum electric distance or maximum signal path length allowed between such components, which need to have a quick communication with each other, the components have been made smaller and smaller and they have also been packed more and more densely. Thus, electronic multi-chip modules have been developed, which permit a very dense packaging of unencapsulated integrated circuits, ICs, or chips. In fact, the signal distances between different active and passive components in such modules do not become much larger than in the case where the whole system had been integrated monolithically on a single chip.
However, the maximum distance, which is determined by the performance requirements set for a considered system, between components which need to communicate with each other, becomes unnecessary restricted in a complex system if only one plane of interconnected chips and/or components can be used, since only components in this single plane then can be reached within the maximum distance.
In order to overcome this problem, three-dimensional or multi-level multi-chip constructions can be used. This means that the communication lines extending from a considered component can not only reach components in the same plane of a multi-level multi-chip module but also components in planes located above and underneath the component can be directly accessed through short signal paths.
This can be obtained in some different manners. Conventional systems having modules such as circuit boards connected to a back plane are in a sense three-dimensional. However, they do not fulfill the above discussed requirement of short signal paths between all those components, which need to communicate with each other. This can not be achieved when components which are close in space are connected by long lines, which obviously becomes the case when two components are connected according to these conventional systems. Also stacks of two-dimensional multi-chip modules having interconnections at the side of the stacks result in long signal paths. If a signal connection between two centrally located components on two different neighbouring multi-chip module planes in such as stack is to be obtained, they are thus connected through a lateral path, a short vertical path at the side of the stack and then a final lateral path on the other plane, adding up to a relatively long distance compared to the case where they are connected for instance directly through a hole in one of the substrates.
Systems are also used comprising a multitude of chips glued together to form a tower or stack and having vertical connections at the side of the chip stack. If more than one stack of chips are used, which have a central or a bottom electrical connection, there can also be problems in arranging short signal paths between the chips. Consider for example the case of two chips located next to each other, but on the top of each pile, which are to communicate with each other. There may also be cooling problems associated with such chip piles.
In order to solve this problem for the case where several two-dimensional multi-chip modules are piled on top of each other forming a three-dimensional multi-chip module, vertical interconnections between the planes located on top of each other have to be formed.
If the vertical interconnections are located closely enough, chips of one plane can not only have a direct contact by means of a short electrical or optical line with its neighbours on the same plane but also with its neighbours above and below. This is a major advantage in the case where components on different planes need to communicate, since the length of the signal paths between such components can be significantly reduced and hence more complex systems can be built, which still meet the requirement of short signal paths between components communicating with each other.
Thus, U.S. Pat. No. 5,371,654 discloses a three-dimensional multi-chip module structure having interconnection means provided in the structure for obtaining vertical interconnections between adjacent assemblies formed by substrates having electrical devices disposed thereon. The interconnection means are made of an elastomeric material having a plurality of electrical conductors extending therethrough, and the interconnection means are made to electrically connect two different adjacent assemblies by compressing the stack of assemblies, the compressive force, in the finished structure, being derived from the fact that the edges of the substrates are inserted in grooves in heat dissipation blocks located at the sides of the structure. The heat dissipation is obtained by manufacturing the substrates of the assemblies of a material having a high thermal conductivity so that the heat will be conducted to the edges of the substrates, where it is carried away by the heat dissipating cooling blocks.
U.S. Pat. No. 5,016,138 discloses a three-dimensional integrated circuit package in which integrated circuit chips are attached to electrically isolating substrates having conducting traces, the electrical connection to the traces being made by wire bonding or flip-chip bonds. A frame surrounds the chips located on a surface of a substrate. Heat sink members made of metal or another heat conductive material, which typically also conducts electrical signals, are inserted between the substrates and the free surfaces of the chips and are located to be in contact with those surfaces of the substrates to which no integrated circuit chips are attached. In the case where the chips are flip-chip bonded to the substrates, a thermally conducting bond, commonly eutectic, can be formed in the space between the back surface of the chips and the heat sinks. Otherwise, metal slugs can be embedded in the substrate in appropriate locations underneath the respective chips for conducting heat from the chips to the heat sinks.
U.S. Pat. No. 5,051,865 discloses a multi-layer semiconductor device including a stacked wafer body. A stack is formed of base unit structures, each comprising an aluminum plate having a silicon wafer on each one of its two large surfaces. The base unit structures are attached to each other by silicone resin, the resulting stack being essentially solid and compact, having no voids and not allowing an easy dismounting of the device.
In U.S. Pat. No. 5,426,563 a three-dimensional module for housing a plurality of integrated circuit chips is described. The structure has communication bars, which also serve as spacers between adjacent substrates of the module. This arrangement provides cooling channels, in which a cooling fluid is present.
In U.S. Pat. No. 5,329,423 an electrically and mechanically connected assembly is disclosed which can be a chip package and can be used in forming multi-chip modules. A bump-and-socket arrangement provides a degree of self-alignment and allows the members to be demountably attached to each other. A similar arrangement of cooperating bumps and recesses is disclosed in the published European patent application 0 439 134 A2 used for packaging a semiconductor device.
Finally, U.S. Pat. No. 5,241,450 also discloses a plurality of multi-chip modules stacked on top of each other.
However, the structures described above suffer from a number of major drawbacks. In particular these drawbacks are related to their thermal dissipation means and to the manner in which the structures are mounted.
Thus, the arrangement comprising cooling means arranged at the lateral sides of the three-dimensional multi-chip module, where the end surfaces of the substrates are located, makes it difficult or impossible to easily and directly connect the module to another three-dimensional multi-chip modules of the same kind at a side provided with cooling means arranged in that way. Therefore, if several three-dimensional multi-chip modules are to be interconnected to form a larger system, the system cannot be built very compact, which today, as stated above, often is a requirement in itself.
Furthermore, the structures and/or the individual chips are in many cases basically fixedly or rigidly mounted to each other. This becomes a problem when an integrated circuit or an entire plane of a three-dimensional multi-chip module is to be replaced, since the procedure of replacement can damage other components of the three-dimensional multi-chip module.